Alta Ares is an air defense Neoprime. We build AI-guided interceptors to counter drones and cruise missiles, along with the software platform that powers them.
Our customers are NATO-aligned militaries and defense institutions, and our systems are regularly deployed during live exercises and operational demonstrations across Europe, the Middle East, and Asia.
Founded in 2024, we have grown to 90 people, raised over $60M, and increased revenue 40× this year. We are now entering a new phase of international expansion, industrial scaling, fundraising, and product development.
Turn radar sensing requirements into FPGA designs that support reliable drone detection in operational conditions.
Define how radar data is acquired, processed, and delivered to the rest of the system, working across RF, electronics, and software teams.
Establish processing budgets and select implementation approaches based on detection performance, latency, numerical accuracy, and available FPGA resources.
Develop reference models to study radar behavior in noise and clutter and guide hardware design decisions.
Build reusable RTL functions for waveform generation and receive processing in FMCW and pulsed radar systems.
Implement the processing stages needed to extract targets from radar returns, including matched filtering, pulse compression, range-Doppler processing, clutter rejection, and CFAR detection.
Integrate ADC/DAC interfaces, coordinate transmit and receive timing, and ensure synchronization with the radar front end.
Specify how detections and associated measurements are passed to tracking functions and embedded software.
Verify designs against reference models through automated testbenches and hardware-in-the-loop testing.
Investigate performance gaps on target hardware and use laboratory measurements and field results to improve the processing chain.
Document design decisions, interfaces, and validation results to support integration and future product development.
At least three years of FPGA development experience, with practical exposure to radar or sonar processing.
Ability to take a signal-processing function from an algorithmic description to verified RTL in VHDL or Verilog/SystemVerilog.
Strong DSP foundations, including FFT, digital filtering, windowing, and the effects of quantization and fixed-point precision.
Understanding of how radar systems estimate target range and velocity, distinguish returns from clutter, and set detection thresholds.
Working knowledge of matched filtering, pulse compression, range-Doppler maps, and CFAR techniques.
Familiarity with FMCW and pulsed radar, including the relationship between waveform choices, acquisition timing, and digital processing.
Experience assessing radar performance through simulation, including signal-to-noise ratio and clutter effects.
Experience developing testbenches, debugging FPGA hardware, and validating processing chains with hardware-in-the-loop methods.
Master’s degree or equivalent in Electrical Engineering, Signal Processing, Applied Physics, or a related field.
Hands-on engineer motivated by making radar processing work reliably on physical hardware.
Able to connect system-level performance issues with their causes in algorithms, RTL, interfaces, or timing.
Methodical approach to debugging, verification, and documenting technical decisions.
Comfortable owning development tasks and coordinating integration work across disciplines.
Clear communicator who makes trade-offs explicit and flags risks early.
Entrepreneurial mindset with the ability to operate autonomously in a fast-growing company.
High integrity and professionalism in handling sensitive defense technologies.